The present invention relates to a memory access control system and, more particularly, to a memory access control system which is suitable for an information processing apparatus having a main memory and a buffer memory.
In information processing apparatuses in which a high speed data processing performance is required, a buffer memory which can read/write data at a higher speed than a main memory is provided in the apparatus, and duplicates of partial data blocks which are frequently used among the data blocks stored in the main memory are provided in the buffer memory, thereby making it possible to promptly respond to an access request from a CPU. As an information processig apparatus having a buffer memory, such an apparatus is disclosed in the specification of, for example, U.S. Pat. No. 3,735,360, "High Speed Buffer Operation In a Multi-Processing System", or U.S. Pat. No. 3,829,840, "Virtual Memory System".
In such an information processing apparatus of the buffer storing system, it is necessary to allow the updating of the data performed in the buffer memory to be reflected into the main memory. Hitherto, in the access system called "store-through", whenever the store access is generated in the data blocks in the buffer memory, data is also stored into the corresponding data blocks in the main memory. According to this system, the advantage of the buffer memory is lost since the number of access times to the main memory increases.
Further, there is known a system, as a "store-in" system, whereby in the case where the necessary data block to be accessed exists in the buffer memory when the data store/access request is generated, the data is stored only into the buffer memory and the content of the main memory is not updated at this time. In the store-in system, a change bit table to store the bit indicating whether data was updated or not is provided in correspondence with each data block in the buffer memory. When it is necessary to swap in the new data block (II) from the main memory in place of one data block (I) in the buffer memory, if a change indication bit is set relative to the data block (I) in the foregoing table, the swap-in operation of the data block (II) is performed after the data block (I) is swapped out to the main memory. If the change indication bit is not set, the swap-out of the data block (I) is omitted and the data block (II) is transferred into the buffer memory. According to this store-in system, the memory access request from the CPU can be satisfied by merely accessing the buffer memory without accessing the main memory until the data blocks in the buffer memory are swapped out to the main memory, so that the data can be processed at a high speed.
However, in the foregoing conventional information processing apparatus of the buffer storing system, in the case where the data in the address to be stored or accessed does not exist in the buffer memory, the whole single data block including this data is transferred from the main memory to the buffer memory and thereafter it is stored into a predetermined address in the buffer memory. Therefore, in the processing apparatus in which, for instance, one data block consists of 64 bytes and which transfers data D.sub.0 to D.sub.7 from the main memory into the buffer memory on an 8-byte unit basis at every machine cycle, there is the following problem. That is, in the case where a full-store request is generated with respect to the data D.sub.0 and D.sub.1 of 16 bytes, conventionally, as shown in FIG. 1, the data registers cannot be released and the next request cannot be received until the writing operations of the data D.sub.0 and D.sub.1 from the store requested data registers are finished after completion of the writing of the last data D.sub.7 read out from the main memory into the buffer memory.